This invention relates to volatile memory elements, and more particularly, to presetting and resetting volatile memory elements on integrated circuits such as programmable logic device integrated circuits.
Integrated circuits often contain volatile memory elements. Typical volatile memory elements are based on cross-coupled inverters (latches) and are used to store data. Each memory element can store a single bit of data.
Volatile memory elements are often used to store configuration data in programmable logic devices. Programmable logic devices are a type of integrated circuit that can be customized in relatively small batches to implement a desired logic design. In a typical scenario, a programmable logic device manufacturer designs and manufactures uncustomized programmable logic device integrated circuits in advance. Later, a logic designer uses a logic design system to design a custom logic circuit. The logic design system uses information on the hardware capabilities of the manufacturer's programmable logic devices to help the designer implement the logic circuit from the resources available on a given programmable logic device.
The logic design system creates configuration data based on the logic designer's custom design. When the configuration data is loaded into the memory elements of one of the programmable logic devices, it programs the logic of that programmable logic device so that the programmable logic device implements the designer's logic circuit. The use of programmable logic devices can drastically reduce the amount of effort required to implement a desired integrated circuit design.
Programmable logic device memory elements are organized in arrays. An array typically contains a number of banks of memory elements. The memory element array can be reset (cleared) by loading logic zeros into the banks. Reset operations are generally performed using clear transistors. With conventional programmable logic device memory arrays, each memory element has an associated clear transistor. When it is desired to reset the memory elements in the array on power-up or before loading configuration data, the clear transistors are turned on and zeros are loaded into the memory elements.
The clear transistors in conventional memory elements consume valuable circuit real estate. Moreover, memory element architectures using clear transistors are susceptible to surge currents during reset operations.
It would therefore be desirable to provide ways to perform operations such as programmable logic device memory element reset operations without consuming excessive circuit real estate or producing surge currents.